A Comparative Analysis of RISC-V Architecture Based on the RISC-V SoC DV Experience
summary
Lab SoC verification replaces an ARM CPU with a RISC-V core, boots Linux, and measures PPA and stability against ARM; compressed instructions generate ~45% 16‑bit ops and yield about 22% code-size reduction, performance varies but power and area look competitive. Experiment implements custom system instructions and finds a custom instruction power-state instability (W mode) and missing CSRs that break software visibility, so verification tooling and standardized system‑level specs are urgently needed.
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chapters (8)
- 0:00Introduction to RISC-V experience
- 1:23Advantages of RISC-V L5 ISA
- 6:15PPA benefits and reliability concerns
- 9:06Customization and market competition
- 12:19Standardization and ecosystem challenges
- 15:39Open source ecosystem comparison
- 17:08Future potential and confidence in RISC-V
- 19:02Q&A session
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