The Genius of RISC-V Microprocessors
summary
Explains why RISC‑V is modular not monolithic, claims the base RV32I spec is tiny enough to read in hours and extensions are frozen for compatibility; shows practical tools (Cornell simulator, Spike, GCC/Clang, Godbolt) and performance tradeoffs: x86 ≈1500 instructions vs ARM ≈1000, RISC‑V can cut die area for microcontrollers, and a real design — ets oc1 from Esperanto — packs 1088 cores plus 4 host cores and runs under ~20 watts, positioning it as a working GPU alternative for ML.
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chapters (18)
- 0:00Start
- 1:05Risk 5 Logo
- 3:58Incremental Instruction Sets
- 5:53Modular Instruction
- 7:40Complexity Cost
- 10:23Control Status Registers
- 13:06Instruction Set Architecture
- 14:31Iot Internet of Things
- 15:13Super Computer on a Chip
- 20:21Vector Processing
- 22:59Overview
- 23:47Pseudo Instructions
- 24:44Arithmometer
- 27:22Assembly Instruction
- 35:18Micro Operations
- 37:13Super Scalar Microprocessors
- 41:51Macro Operation Fusion
- 42:59Smart System
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