Could RISC-V Become a Force in HPC?
summary
Claims a production-ready RISC-V stack: a 64-bit AX65 core (RV64GC) with 13-stage pipeline, up to eight cores, quad-issue and 128‑entry ROB, and an AX45MPV application core with 32‑register vector unit, 12 vector functional units and VLEN configurable to 128–1024 bits. Shows a 7 nm Chilai dev board running Linux and TinyYOLO, an NDLA INT8 accelerator with onboard memory (16 KB–4 MB), HBM-style local memory path, and working software toolchain and libraries.
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chapters (9)
- 0:00Introduction to RISC-V in HPC
- 2:12Andes AX65 high-performance CPU core
- 3:58Andes AX45MPV vector core features
- 11:48High-bandwidth vector local memory
- 13:16Andes A350 platform integration
- 14:43Qilai development platform overview
- 15:05Andes deep learning accelerator
- 18:35Summary and RISC-V future in HPC
- 19:18Q&A session
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