Boosting AI on Semidynamics RISC-V Cores with Custom Tensor Instructions

on YouTube ↗10m

" summary

Proposal: a single RISC‑V element combining an out‑of‑order Atrio R5 core, an out‑of‑order vector unit supporting RVV 1.0 and a configurable tensor unit (0.25–8 TOPS per tensor instance) to avoid NPUs/GPUs, single Linux software stack, and no DMA copies. One element at ~1 GHz runs YOLO at 33 fps, scale by tiling identical cores to reach target TOPS. IP ships for FPGA prototyping, customization and tape‑out support.

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" chapters (7)

1. 0:00Introduction
2. 1:00The problem with RISCV architecture
3. 2:50The solution
4. 5:53Running Linux
5. 7:52Benchmarks
6. 8:24Conclusion
7. 9:11Outro

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