Accelerating Edge AI with the Help of RISC-V
summary
A European startup integrates RISC-V as the control plane for an in‑memory AI datapath, taped out Metis in 12 months and boots the first RISC-V core within hours of silicon return. The product repeats an AI core four times, adds a system controller and a root‑of‑trust — six RISC-V cores in total — and ships on PCIe M.2 cards and vision appliances. Development uses Spike and QEMU for full‑system emulation and rapid bring‑up (used Spike and QEMU). Pain points: cache/ECC handling and differing atomic implementations that risk subtle vendor lock‑in.
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chapters (5)
- 0:00Introduction and background
- 3:31Product architecture overview
- 7:24Advantages of RISC-V
- 12:39Challenges with RISC-V
- 16:24Results and future plans
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