Accelerating Designs for SoC FPGA Using Simplified High-Level Synthesis Flows
summary
Demonstration builds an end-to-end H.264 network streamer on a Microchip PolarFire SoC RISC‑V + FPGA using Microchip’s Smarts HLS to convert C++ functions into AXI‑connected accelerators with autogenerated driver APIs and embedded DMA bursts. The FPGA pipeline sustains ~33 fps while CPUs remain idle; running the same transforms on RISC‑V drops to ~28–29 fps for simple cases and to ~6–7 fps or below 1 fps when complex or single‑threaded, while network bandwidth spikes from ~2.5 to 10 MB/s. Example code and integration scripts are on GitHub.
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chapters (8)
- 0:00Introduction to SoC FPGA challenges
- 2:09High-level synthesis benefits
- 4:20Example application overview
- 6:05Code example and pragmas
- 9:34Software integration details
- 11:21Testbench and validation
- 11:43Live demo walkthrough
- 16:22Summary and future outlook
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