Introduction to Project CHERIoT

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" summary

CHERIoT implements a CHERI-derived RV32 ISA extension (about 30 new instructions) that represents capabilities as a 65-bit tagged structure and enforces spatial memory safety, temporal memory safety, and fine-grain compartmentalization in hardware. It ships an LLVM-based compiler/linker/debugger, an RTOS reference design, and a production-quality Ibex-derived core RTL called Chariot Ibex; silicon-area rises about 5–10% versus baseline Ibex, performance and power remain similar, and Oxford formal verification plus randomized RTL simulation validate instruction correctness.

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" chapters (9)

1. 0:00Introduction to CHERIoT
2. 2:47Why CHERIoT exists
3. 4:58Core security claims
4. 8:57Capabilities explained
5. 11:51CHERIoT Ibex core
6. 14:28Hardware evaluation
7. 15:53CHERIoT IPG platform
8. 17:47Software development flow
9. 20:21Resources and next steps

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