Ventana’s Second Generation RISC-V Processor for Data Center and Other High Performance Applications

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" summary

Veyron V2 is a 32‑core RISC‑V chiplet/IP aimed at data center and HPC with a claimed 40% IPC uplift over V1; each core has ~1.5 MB of private L1-style cache, a cluster up to 120 MB shared L3, and a macrop‑op cache that matches a ~32 KB L1i hit rate. The core frontend dynamically decodes 5–15 wide into up to 16 executions per cycle, implements RVV 1.0 with 512‑bit vectors, and ships over UCI/CHI chiplet links (4×~120 GB/s).

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" chapters (10)

1. 0:00Introduction and markets
2. 1:00Performance and chiplets
3. 2:39Core architecture features
4. 4:35Microarchitecture details
5. 7:34Macro ops and execution
6. 10:05Load, store, and cache
7. 11:56Vector unit capabilities
8. 13:55Cluster level L3 cache
9. 15:21Chiplet layout and security
10. 17:30Q&A session

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