KEYNOTE: RISC-V: Enabling a New Era of Open Data-Centric Computing Architectures

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" summary

Western Digital commits its storage business to RISC‑V and builds a first SoC around an RV32IMC core (2‑way superscalar, nine‑stage pipeline) intended as a NAND flash controller for consumer SSDs, targeting tape‑out in a couple months. The company cites custody of ~50% of world data, shipping about a billion CPU cores a year, chooses 28 nm for the initial part, and emphasizes innovation outside the core (custom buses, IP, error‑correction engines). Implementation is underway; results are pending the tape‑out.

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" chapters (17)

1. 0:00Introduction and event context
2. 1:05Western Digital’s RISC-V commitment
3. 3:54Data value and fast vs big data
4. 6:02Western Digital as data custodian
5. 7:25Limitations of general-purpose CPUs
6. 9:34Why RISC-V for data-centric computing
7. 10:56First RISC-V implementation in flash controllers
8. 12:19Flexibility and innovation with RISC-V
9. 13:44RISC-V for embedded and enterprise
10. 15:31RISC-V in edge and big data analytics
11. 16:36Building RISC-V ecosystem momentum
12. 18:22Security and edge analytics with RISC-V
13. 19:24Advantages of open RISC-V architecture
14. 20:27Industry and academic support for RISC-V
15. 21:10Western Digital’s RISC-V roadmap
16. 22:32Call to innovate with open architecture
17. 22:54Q&A on RISC-V implementations

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