Architecture Exploration of RISC-V Processor and Comparison with ARM Cortex A53 and A72
summary
Presents an architecture exploration of a RISC‑V processor and compares its performance and design characteristics with ARM Cortex‑A53 and Cortex‑A72. Covers concrete metrics and architectural differences used for that comparison, as presented by Karthikeyan Sugymaran and Tom Jose at the RISC‑V Workshop Chennai 2018.
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chapters (13)
- 0:00Start
- 0:13Problem
- 2:53RISC-V Processor Specs
- 3:30VisualSim Schematic
- 5:21Results - Task Latency
- 5:50Results - Task Set Latency
- 7:34Results - Average Power Consumption
- 8:00A53 Specs
- 9:01Task Set Latency Task Set Latency
- 9:40Power Consumtion
- 11:55Read/Write Latencies and Average Power.
- 13:08Future Development
- 13:29Conclusion
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