~/talk

Architecture Exploration of RISC-V Processor and Comparison with ARM Cortex A53 and A72

Talkat RISC-V Workshop Chennai 2018 · 2018-07-18..07-19· [embedded-and-hardware]
links:none on file
name:Tom Jose
links:none on file
slides:none on file

Presents an architecture exploration of a RISC‑V processor and compares its performance and design characteristics with ARM Cortex‑A53 and Cortex‑A72. Covers concrete metrics and architectural differences used for that comparison, as presented by Karthikeyan Sugymaran and Tom Jose at the RISC‑V Workshop Chennai 2018.

AI-written summary · about

  1. 0:00Start
  2. 0:13Problem
  3. 2:53RISC-V Processor Specs
  4. 3:30VisualSim Schematic
  5. 5:21Results - Task Latency
  6. 5:50Results - Task Set Latency
  7. 7:34Results - Average Power Consumption
  8. 8:00A53 Specs
  9. 9:01Task Set Latency Task Set Latency
  10. 9:40Power Consumtion
  11. 11:55Read/Write Latencies and Average Power.
  12. 13:08Future Development
  13. 13:29Conclusion
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