A Survey of E31 RISC-V Core Floor-Plan and Its Impact on Power, Performance and Area (PPA)

on YouTube ↗41m

" summary

Survey shows a practical floor‑planning method that breaks the E31 core into hierarchical subblocks, runs synthesis with Yosys, placement with TimberWolf/Qflow, routing with Qrouter, and timing with Vesta (OpenTimer coming). A flat full-chip run yields ~74 MHz, while hierarchical isolation raises the slowest block to about 240 MHz (and picoRV32 moves from ~275 MHz to ~400 MHz, ~1.5x). Team also demonstrates a flat tape‑out on X‑FAB 180 nm using the open-source EDA flow.

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" chapters (9)

1. 0:00Introduction and VSD mission
2. 2:34Floor planning fundamentals
3. 6:30Advanced timing analysis
4. 9:01Hierarchical design of E31
5. 14:20Results and performance
6. 18:35Scaling to PicoRV32
7. 22:19Open source EDA roadmap
8. 27:01Q&A and EDA ecosystem
9. 31:14Community outreach and VSD

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