RISC-V CPU Project in Western Digital

on YouTube ↗43m

" summary

Western Digital develops a RISC-V core ECHX1 as a 2-way superscalar 9-stage pipeline implemented in TSMC 28 nm reaching ~970 MHz (target 1 GHz) and occupying ~0.09–0.15 mm^2, showing 4.9 CoreMark/MHz with a 2048-entry BTB; multiply is 2-cycle, divider ~31-cycle, compressed-instruction support and configurable custom op space. Research prototypes pack TileLink into L1 Ethernet frames with a P4 switch (MPF4brik) and measure ~432 ns path latency and ~1.8–2 µs remote-memory accesses; RTL and tools are planned for upstream open-source release.

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" chapters (17)

1. 0:00Intro
2. 3:44What's Different about RISC-V?
3. 5:31RISC-V for IoT/embedded
4. 9:17Western Digital: key requirements
5. 11:36Western Digital RISC-V Core
6. 13:24Core Microarchitecture
7. 15:55Branch prediction
8. 17:19Physical design
9. 18:43Performance
10. 22:08NAND Controller SoC applications
11. 28:01Vision for future datacenter CPU architecture
12. 32:34Emergence of memory fabrik
13. 35:24Latency requirements
14. 36:18Latency measurements with Barefoot Networks Tofino
15. 37:55MPF4brik memory centric architecture
16. 38:45P4 example: MPF4brik programmable switch
17. 40:36Accelerating the RISC-V Ecosystem

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