Keynote: Unleashing the Power of Data with RISC-V

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Western Digital prototypes two in-house RISC‑V cores (a tiny and a small) targeted at SSD controllers, each implemented as a 2-way superscalar in‑order core with a 9-stage pipeline. Cores already connect to an ECC engine and the NAND channel, are in test and validation, and aim for product sampling in early 2019. Design avoids full speculative execution, uses microarchitecture tweaks plus a few custom instructions, and may be open‑sourced after sanitizing proprietary uncore interfaces.

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