Keynote: Racing to Adoption: From Momentum to Mainstream with RISC-V

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" summary

Ventana announces V2 as a follow-on CPU that pushes IPC about 40% over V1, adds full vector support, a three‑level cache (1.5 MB private per core, up to 120 MB cluster), scaling up to 192 cores, and a chiplet strategy using a UCI die‑die interconnect. The platform bundles tightly‑coupled domain‑specific acceleration with a compiler/SDK that makes DSA transparent to workloads, includes enterprise RAS (data scrubbers, data‑poisoning) and secure boot, and targets data center, HPC, automotive, edge and mobile.

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" chapters (15)

1. 0:00Introduction
2. 0:42Welcome
3. 3:07Market segments
4. 6:59Going from momentum to mainstream
5. 9:26Weon V2
6. 10:40RISCV Architecture
7. 11:22Cache Hierarchy
8. 11:39High Performance
9. 12:05Enterprise Class Raz
10. 12:22Security
11. 12:44Chipet
12. 13:20Moors Law
13. 13:48System Level IP
14. 14:03Software Ecosystem
15. 14:21Conclusion

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