RISC-V IOMMU

on YouTube ↗24m

" summary

Specification ratified this year that defines a system IOMMU for RISC‑V implementing two-stage address translation with per‑transaction device and process directories (device ID is 16 bits), an address translation cache (ATC), asynchronous command and fault/event queues, PCI ATS/PRI support and a MSI page table for direct guest interrupt delivery. It enables secure device passthrough, shared virtual addressing for pointer sharing with accelerators, page request/response flow, up to 64 hardware interrupt files, 31 programmable event counters, and multiple integration models.

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" chapters (13)

1. 0:00Introduction to RISC-V IOMMU
2. 1:24Key IOMMU capabilities
3. 3:11IOMMU use cases explained
4. 6:41Two-stage address translation
5. 8:27Address translation caching
6. 10:13Handling faults and page requests
7. 11:37Recoverable faults with ATS
8. 14:03Direct interrupt delivery
9. 16:54Memory resident interrupt files
10. 17:56Hardware performance monitoring
11. 18:37Endianness and ISA support
12. 20:02IOMMU system integration
13. 22:07Summary and capabilities

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