RISC V Memory Consistency Model Task Group Update
summary
Task group upstreams a concrete memory model: RVWMO baseline defines same-address ordering, load-value, atomicity (LR/SC) and a progress axiom, plus syntactic address/control/data dependencies and a ban on non‑speculative forwarding from atomics; RVTSO extension offers an x86‑like TSO option; Zam misaligned AMOs separates limited misaligned-atomic support; three formalizations and 7,000+ litmus tests appear online; the spec enters a 45‑day ratification window and tooling (herd, Alloy, operational models) already validate designs and guide fence/implementation choices.
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chapters (8)
- 0:00Introduction and goals
- 1:43Task group formation and decisions
- 3:27Current specs and ratification
- 4:48Memory model fundamentals
- 7:16Rules and axioms in RVWMO
- 11:08Extensions Ztso and ZAM
- 12:53Appendices and resources
- 13:57Future work and ratification timeline
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