Fast Interrupts for RISC-V
summary
New task group defines concrete fast-interrupt changes: add configurable per-interrupt privilege/mode, preemption level (3–7 suggested) and priority, provide hardware or software stacking so nested interrupts save MCAUSE/MEPC/MSTATUS without full context swaps, and support tail-chaining and MSI scaling. Current pain points: PLIC forces two memory accesses (claim and complete) and vector table uses 4-byte vector entries with only ±1MB jump range, while UNIX ABI forces saving many registers. Proposed fixes include inline GCC handlers, hardware stack frames, and an instruction-mode vectoring trick to avoid pipeline rewrites.
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chapters (16)
- 0:00Intro
- 1:33Summary of Current RISC-V Interrupts
- 2:58Current RISC-V Interrupt Overview
- 4:47Machine Interrupt Pending (mip) CSR
- 5:00Machine Interrupt Enable (mie) CSR
- 5:26Interrupts in mstatus
- 6:20Interrupt reported in mcause CSR
- 7:09Machine trap-vector base (mtvec) CSR
- 9:14Saving/Restoring Interrupted Context
- 10:10Problems with Current Interrupts
- 14:18Input from Multiple Proposals
- 16:32Interrupt Handler Interfaces
- 17:52Inline interrupt Example
- 21:02Vectoring Options
- 23:54Interrupt Mode, Level, Priority
- 26:33Other issues
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