Smallest RISC-V Device for Next-Generation Edge Computing

on YouTube ↗15m

" summary

A 14 nm RISC‑V system shrinks a processor die to ~0.07 mm² with a separate 32 KB SRAM die (~0.04 mm²) and a <1 mm² silicon interposer using 20 µm bumps for 2.5D integration. On‑chip SRAM reduces to ~2 KB, instruction memory moves to external flash over an 8‑bit SPI bus because of a 30‑pad limit, and a hardware SHA-256 auth engine yields ~20× faster auth. Communication uses an optical micro‑LED UART with HDLC framing; first silicon boots, accepts app upload and runs.

AI-written summary · about

" chapters (8)

1. 0:00Project goals and background
2. 1:34System design requirements
3. 3:15First-generation architecture
4. 4:38Memory and performance tuning
5. 8:02Hardware acceleration
6. 9:40Testing and validation
7. 11:37Future outlook and conclusions
8. 13:36Q&A and technical rationale

" related talks

• 01h 01mThe Genius of the RISC-V MicroprocessorErik Engheim · NDC TechTown 2021
• 13mUsing RISC V As a Security Processor For DARPA CHIPS And Commercial IoTMark Beal · 7th RISC-V Workshop 2017
• 01h 01mThe Genius of RISC-V MicroprocessorsErik Engheim · ACCU 2022
• 15mSERV: 32-bit is the New 8-bitOlof Kindgren · RISC-V Summit 2022
• 08mSERV: RISC-V for a Fistful of GatesOlof Kindgren · RISC-V Forum: Embedded Technologies 2021
• 43mRISC-V CPU Project in Western DigitalZvonimir Z Bandić · ORConf 2018
• 19mAccelerating Edge AI with the Help of RISC-VFlorian Zaruba · RISC-V Summit North America 2023
• 20mCould RISC-V Become a Force in HPC?Niraj Dengale · RISC-V at embedded world 2024