SERV: 32-bit is the New 8-bit
summary
SERV claims to be the world's smallest RISC-V CPU, implemented as a bit-serial 32-bit core that trades gates for cycles, shrinking logic to roughly a bit over 2k gates (excluding register file) and enabling 10,000+ cores on an FPGA. It runs Zephyr and even Doom on reference platforms, is used for DDR init, logging and a cranial implant and radar SoC, and ships student projects adding an AI CFU and a printable-electronics tapeout while proposing an RF-in-RAM extension to save register area.
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chapters (10)
- 0:00Introduction to Serve
- 0:51Overview of Serve features
- 1:32The bit-serial architecture
- 2:35Physical size and benchmarking
- 3:38Documentation and validity
- 4:11Use cases and integration
- 6:07Proposed memory optimizations
- 7:44Current and future development
- 8:38Future architectural plans
- 10:04Q&A session
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