Olof Kindgren
where else to find them
what they talk about
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where they keep going back
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on a stage with
never shared a talk
who talks about the same things
- Karol Gugala12 talks
- Drew Fustini21 talks
- Michael Gielda25 talks
- Stefan Wallentowitz15 talks
- Peter Birch3 talks
- Stephano Cetola6 talks
| title | conference | date |
|---|---|---|
| FuseSoC for large real-world code bases | Latch-Up 2026 | 2026-05-01 |
FuseSoC is a 15‑year package manager that already catalogs over a thousand public cores and scales to company repos with thousands more (one example is ~3,000… | ||
| Beyond EDA lies Edalize | Latch-Up 2024 | 2024-04-19 |
Edalize is a standalone Python library that programmatically builds and runs EDA workflows by turning an Edam format description into tool-specific setups… | ||
| CoreScore like never before | Latch-Up 2024 | 2024-04-19 |
CoreScore measures how many RISC‑V SERVE cores fit into various FPGAs and claims a surprising top result of 10,000 RISC‑V cores packed onto a large AMD board… | ||
| FuseSoC in Three Minutes | ORConf 2023 | 2023-09-15 |
FuseSoC is a package manager for silicon that dates to 2011 and is already used by many high‑profile open source chips and several companies internally so it… | ||
| SERV - A quick talk about a small CPU | ORConf 2023 | 2023-09-15 |
A tiny RISC-V-like core uses a bit serial datapath and optional extensions with separate data and instruction buses and an extension interface, documented to… | ||
| SERV: 32-bit is the New 8-bit | RISC-V Summit 2022 | 2022-12-13 |
SERV claims to be the world's smallest RISC-V CPU, implemented as a bit-serial 32-bit core that trades gates for cycles, shrinking logic to roughly a bit over… | ||
| A CPU is Only as Good as its Ecosystem: Turning RISC-V CPUs into Systems with FuseSoC- | Spring 2022 RISC-V Week — RISC-V International Day | 2022-05-05 |
FuseSoC is a package manager for IP cores that turns RISC-V CPU RTL and third‑party cores into buildable systems, resolving version constraints and complex… | ||
| SERV: RISC-V for a Fistful of Gates | RISC-V Forum: Embedded Technologies 2021 | 2021-07-21 |
SERV claims the title of smallest RISC‑V CPU and keeps shrinking with recent optimizations, now ported to more than 30 FPGA boards and demonstrably taped out… | ||
| Welcome to ORConf 2019 | ORConf 2019 | 2019-09-27 |
Welcome note that traces open‑source silicon from 20 years since 1999 through a 2002 commercial spike (Flextronics), a 2008 revival (ORSoC buying OpenRISC)… | ||
| FuseSoC | Week of Open Source Hardware 2019 | 2019-06-13 |
FuseSoC is a package manager and build system for HDL that flattens dependency trees, generates tool-specific setup scripts (Tcl, project files), and can run… | ||
| Open Source Silicon: Where software ends and hardware begins | foss-north 2017 | 2017-04-26 |
Open source silicon covers building complete chips using free RTL, toolchains and workflows to avoid vendor lock‑in while gaining lower cost, auditability and… | ||
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