SERV: RISC-V for a Fistful of Gates
Talkat RISC-V Forum: Embedded Technologies 2021 · on Wednesday, 2021-07-21· at 09:45· Virtual 1, Virtual·
summary
SERV claims the title of smallest RISC‑V CPU and keeps shrinking with recent optimizations, now ported to more than 30 FPGA boards and demonstrably taped out via OpenMPW using SkyWater 130 nm, where a Subservant SoC measures 0.01 mm² synthesis and 0.04 mm² P&R. ASAP7 estimates a 7 nm implementation at 94 µm² running 2.4 GHz. Multiplication/division use software by default with an optional external MDU (Google Summer of Code) and the core runs Zephyr 1.14/2.4, simulation of legacy game software, and scales to thousands of cores in large FPGAs.
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chapters (9)
- 0:00Introduction to Serv
- 0:57FPGA support and growth
- 1:56ASIC implementation
- 3:10Discrete logic version
- 3:38Software and ecosystem
- 4:11Performance enhancements
- 5:18Documentation improvements
- 5:44Use cases and benchmarking
- 6:57Smart RAM and conclusion
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