Getting Started with the Free ISS for the OpenHW CORE-V IP Roadmap
Talkat RISC-V Forum: Embedded Technologies 2021 · on Wednesday, 2021-07-21· at 09:55· Virtual 1, Virtual·
summary
Free Imperas RISC-V OVPsim Core-V provides a downloadable, Apache‑2.0 ISS that models CPU and memory for the OpenHW CORE-V family and is configurable for CV32E40P, CV32E40S, CV32E40X and CVA6-32/64. It supports user/privileged specs, vector, bit‑manip and hypervisor extensions, and includes templates to add custom CSRs. Used to verify CV32E40P by instruction‑by‑instruction CSR/GPR/PC compare against RTL driven by Google random tests, it boots a Fibonacci demo via semihosting and debugs with GDB and Eclipse GUI.
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chapters (14)
- 0:00Introduction
- 1:24Key Technology
- 1:37Core Reference Model
- 2:44Base Model
- 3:34Use Cases
- 3:53Design Verification
- 5:18Software Development
- 6:01Fix Virtual Platform
- 6:45GitHub Repository
- 7:01Running the Program
- 7:23Documentation
- 8:48Debugging
- 9:17Eclipse GUI
- 9:38Summary
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