Free and Open Source Hardware to enable RISC-V IoT Applications With
summary
Open-source group ships industrial-grade RISC-V IPs (96 members) and reports the CORE-V CV32E40P at technology readiness level 5. The demo loads a core-v-mcu bitstream from a USB stick onto an FPGA, deploys a FreeRTOS app with an Ashling debug probe via the Core5 IDE (Eclipse CDT), reads an I2C temperature sensor, formats JSON, publishes MQTT to Mosquitto, and visualizes live data in Streamsheets. Tool quirks: Core5 SDK requires Ubuntu 20.04; FPGA emulation differs from final silicon.
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chapters (12)
- 0:00Eclipse Open Hardware Group
- 1:08Open Hardware Group
- 3:18Open Hardware Europe WG
- 5:32RISC-V IP cores overview
- 8:46Core5 MCU ecosystem
- 9:30Demo setup and tools
- 10:53Core5 IDE and firmware
- 14:08Live demo execution
- 17:22IoT data visualization
- 20:59Eclipse and Open Hardware
- 22:48Q&A: RISC-V space/real-time
- 25:48Hardware pricing
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