RISC-V Spotlight: Improving RISC-V Quality with Verification Standards and Advanc...

on YouTube ↗18m

" summary

Claims that full SoC verification drives orders of magnitude more work than most RISC-V teams expect, citing 2.1×10^15 cycles as an Arm reference and showing that simulators or emulators alone would take years or thousands of machines. Describes a reusable testbench and reference-model setup used with OpenHW that reaches RTL freeze, introduces the RVVI trace interface (GitHub) and a machine‑generated functional coverage bundle to replace 40,000 lines of SystemVerilog coverage, and argues standards plus shared tooling cut cost and time.

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" chapters (4)

1. 0:00Introduction and problem statement
2. 3:07Verification challenges in RISC-V
3. 7:21Collaboration and standardization efforts
4. 15:47Call to action and summary

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