RISC-V Spotlight: Ventana Brings RISC-V to Data Center with Veyron V1
summary
Veyron V1 claims to be the first RISC‑V data‑center class CPU: a 5nm multi‑chiplet SOC with a wide out‑of‑order core, 1MB L2 per core and 64MB cluster L3, hardware ECC and side‑channel mitigations, and an on‑package hub that lets customers add accelerators. Bandwidth and latency target 7 ns interconnect (vs ~110 ns today) and scale to up to 128 cores on 5nm (optionally higher with more chiplets). Software ports are said to be production‑ready and targeted markets are cloud, automotive, 5G and edge.
AI-written summary · about
chapters (11)
- 0:00Introduction and welcome
- 1:31Why RISC-V for data centers
- 4:45Key challenges in CPU design
- 7:55Veyron V1 overview
- 8:16Core architecture details
- 11:09Chiplet-based system design
- 12:32Performance and innovation benefits
- 14:14Chiplet advantages explained
- 15:58Software ecosystem readiness
- 17:03Market applications for Veyron V1
- 18:05Future roadmap and community goals