Is RISC-V HPC? RISC-V is HPC!
summary
Claims RISC‑V is ready for HPC with concrete tooling, testbeds and funding: an HPC SIG defines ISA extensions (57‑bit VA, K user/kernel page table), an automated Jenkins CI/CD that builds LLVM/GCC for many targets via risk5test.org, and physical testbeds like SuperFive testbed and Excalibur with off‑the‑shelf boards and emulation (≈100 FPGAs). Projects tape out chips from 65nm down to 12nm with TSMC and GF, a student cluster of 13 boards ran HPL and won fan favorite, and a public 270M EUR call funds RISC‑V HW/SW.
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chapters (6)
- 0:00Intro
- 1:23Mont-Blanc HPC Stack for ARM
- 5:47HPC Software Stack Testbed
- 7:41Public Test Harness
- 13:32RISC-V Hardware Activities
- 14:20RISC-V Software Activities
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21mCo-developing RISC-V Hypervisor Support
30mIntegrating Gen-Z in Server-Class RISC-V Processors
20mAn Automated Scalable RISC-V Cache Coherency Verification Project
22mAn Open and Coherent Memory Centric Architecture Enabled by RISC V
23mBreaking the limits of x86
17mSRNIC: A Scalable Architecture for RDMA NICs