SRNIC: A Scalable Architecture for RDMA NICs
summary
Presents SRNIC, an FPGA prototype RDMA NIC architecture that removes on‑chip structures via protocol header extensions, cache‑free QP scheduling, and memory‑free selective repeat to boost connection density. Implements QPC and MTT only on chip, uses host memory for bitmaps and RIT, and runs at 300 MHz. Achieves 10K performant connections, sustains 97 Gbps and 3.3 μs latency with <5% CPU overhead, and reports 18x normalized connection scalability versus commercial RNICs.
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chapters (16)
- 0:00Intro
- 1:36RDMA becomes the de-facto standard for high-speed networks in modern datacenters
- 2:18Network Scalability Issue
- 3:41Connection Scalability Issue
- 5:19Idea & Design Principles
- 6:13Strategies to Minimize On-chip Data Structures
- 6:41Data Structures Involved
- 8:18Analysis & Optimization Ideas
- 8:51Cache-free QP Scheduler
- 9:45Bitmap Onloading
- 10:44Header Extensions
- 13:06Prototype Implementation
- 13:39Evaluation - Connection Scalability
- 14:32Evaluation - Performance & CPU Overhead
- 14:54Evaluation - Network Scalability
- 15:55Summary
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