DRack: A CXL-Disaggregated Rack Architecture to Boost Inter-Rack Communication
summary
Proposes disaggregating all NICs and memory inside a rack into a shared NIC pool and memory pool accessed with CXL semantics, so any host can drive multiple NIC links concurrently and DMA intermediate data across pooled devices. Implements a software–hardware co‑simulation prototype on eight MPSoC nodes, adds a DMA cache, memory‑interleave placement (ISI/IS0) and MPTCP plus a kernel driver, and shows real workloads (DNN training, graph processing) cut communication time by ≈37.3% on average.
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chapters (9)
- 0:00DRack architecture intro
- 1:45Rack inter-communication challenges
- 4:13DRack concept and pools
- 6:40Key benefits of DRack
- 7:04Latency and programming challenges
- 9:11DRack protocol stack
- 11:20Simulation prototype setup
- 13:52Performance with real apps
- 15:58Summary and future work
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