FLASH: Towards a High-performance Hardware Acceleration Architecture for Cross-silo...
summary
Identifies nine real-world cryptographic operations that dominate cross-silo federated learning and shows they all reduce to two primitives, modular exponentiation and modular multiplication. Implements a prototype on Xilinx VU13P FPGA integrated with FATE and a simulated 12 nm ASIC, and reports up to 14.0× speedup over CPU and 3.4× over GPU on the crypto ops, translating to up to 6.8× end-to-end vs CPU and 2.0× vs GPU; ASIC projection gives 23.6× improvement over the FPGA.
AI-written summary · about
chapters (12)
- 0:00FLASH architecture intro
- 1:46Cross-silo federated learning need
- 3:53Horizontal vs vertical FL
- 5:38Cryptographic operations in federated learning
- 8:31GPU limits for crypto ops
- 9:35FLASH hardware design
- 11:42Modular multiplication engines
- 12:24Optimizing modular exponentiation
- 13:30Dynamic data flow scheduling
- 14:33FLASH framework integration
- 15:19FLASH prototype performance
- 16:46FLASH future potential
related talks
01h 11mMachine Learning Acceleration in an Embedded World
31mCFU Playground
26mAccelerated Quantum Supercomputing and Post-Quantum Cryptography
23mBatchCrypt: Efficient Homomorphic Encryption for Cross-Silo Federated Learning
13mHardware/Software Co-Programmable Framework for Computational SSDs to Accelerate Deep...
43mHigh Speed Query Execution with Accelerators and C++
20mBoosting Video Codec With RISC-V Vector Extension
30mCFU Playground: Model-specific Acceleration on FPGAs