CFU Playground: Model-specific Acceleration on FPGAs
Talkat RISC-V Forum: Developer Tools and Tool Chains 2021 · on Wednesday, 2021-06-02· at 17:15· Virtual·
summary
CFU Playground is an open source framework that lets engineers add a custom function unit to a VexRiscv soft RISC‑V core on FPGA and specialize TensorFlow Lite for Microcontrollers kernels for one model The workflow uses CFU Playground, generates Verilog for any board via VexRiscv + LiteX, and debugs with Symbiflow Renode and Verilator A 1x1 convolution CFU evolves through iterative RTL and kernel changes to reach 5x–60x operator speedup and about 3x overall program speedup on real FPGA hardware
AI-written summary · about
chapters (12)
- 0:00Introduction and overview
- 2:06What is CFU Playground
- 4:33Custom function units explained
- 8:06Software integration with CFU
- 10:56TensorFlow Lite for Microcontrollers
- 13:47CFU Playground setup
- 16:57Software development flow
- 19:28Debugging and simulation
- 20:33First model optimization example
- 23:46Iterative hardware acceleration
- 27:20Current project status
- 27:43Future directions and community
related talks
31mCFU Playground
14mA RISC-V Compatible Systolic Array for TinyML Applications in CFU Playground
11mLightning Talk: The CFU: Custom Hardware with RISCV and Zephyr
24mUniversal Tools for Acceleration, Timing, Integration & Machine Enhancement
43mSoftware Development Trends for FPGAs
34mBuilding FPGA-based Machine Learning Accelerators in Python
18mFLASH: Towards a High-performance Hardware Acceleration Architecture for Cross-silo...
21mA Functional Approach to Synthesizing Routable Programmable Accelerators for Neural(…)