A RISC-V Compatible Systolic Array for TinyML Applications in CFU Playground
summary
A configurable RISC-V compatible systolic array is implemented in CFU Playground as a CFU co-processor and runs on an Arty A7-100T (Artix‑7) FPGA at 100 MHz. A 3×3 array consumes 14% of DSPs and 24% of LUTs while a 10×10 array uses 100% of DSPs and 37% of LUTs. Matrix‑multiply kernels show 2.7× and 9× speedups and energy reductions of 120× and 40× versus software-only execution.
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chapters (7)
- 0:00Introduction
- 0:36Systolic arrays overview
- 2:00CFU Playground framework
- 3:45Performance results
- 5:55Demo setup issues
- 10:08Demo execution
- 11:36Conclusion and future work
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