Spike-RTL: quasi-cycle accuracy hardware/software co-simulation
summary
Spike-RTL replaces processor and memory Verilog with Spike and drives the rest of the platform under Verilator, demonstrated on a modified X-HEEP platform and on an audio noise‑cancellation example using I2S and UART; measured results show roughly 2× speedup with ~6% quasi‑cycle timing error versus full RTL, while standalone Spike is orders of magnitude faster but incurs >20% timing error on simple sequential tests. The integration supports interrupts, bus transactions, waveform visibility and bidirectional DMA plans.
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chapters (8)
- 0:00Introduction and motivation
- 1:20Current simulation approaches
- 3:10Proposed Spike-RTL integration
- 5:37Why Spike for co-simulation
- 7:40Performance results comparison
- 10:31Demo and live results
- 13:04Tool capabilities and future work
- 17:06Conclusion and Q&A
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