Efficient debug and trace of RISC-V systems: a hardware/software co-design approach
summary
A hardware/software co‑design called UltraSoC‑V ships preverified IP (E‑Trace–compliant enhanced trace encoder) that compresses trace to an average 0.2 bits per instruction and gains ~40% more compression with optional extensions. A tailored OpenOCD flavor decodes RISC‑V plus custom instructions; a static instrumentation path is 1–2 orders of magnitude cheaper than printf; a DMA module speeds ELF uploads by 100x DMA speed; a UVM verification IP lets integrators validate connections and functionality before silicon.
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chapters (8)
- 0:00Introduction and context
- 1:07Challenges in RISC-V debugging
- 2:57Co-design methodology
- 4:12Processor trace solutions
- 7:44Static instrumentation
- 9:11Hardware-software features
- 10:51Verification and UVM support
- 12:36Conclusion and Q&A
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