RISC-V open designs and contributions to hardware security research and development activities
summary
ANSSI describes concrete projects: an IPCC ECC hardware accelerator implements ECC with switchable side‑channel and fault countermeasures and runs on a SoC FPGA (ARM) and a full FPGA with RISC‑V CVA6, with a LIC library and a planned full ASIC RISC‑V build. A FEX crypto‑agility module targets MLK and HQC and is being integrated externally to cores for software swap‑out. The France‑2030 ARSEN test chips program builds 32/64‑bit FPGA/ASIC test chips, while a separate project measures robustness and the gap between experiments and formal verification of countermeasures.
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chapters (10)
- 0:00Introduction and welcome
- 1:03Hardware security challenges
- 3:16Security features and evaluation
- 5:05Agency projects overview
- 6:09IPCC ECC hardware accelerator
- 8:20Crypto agility with FEX design
- 9:49ARSON project focus
- 12:21Super Confus Transfer project
- 14:36Project references and closing
- 14:57Q&A on software platform and manufacturing
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