CPU Security in the Context of RISC-V
Talkat RISC-V Summit North America 2024 · on Tuesday, 2024-10-22· at 13:55· Grand Ballroom H (Level 1)·
summary
Secure-IC describes an RTL Cyber escort unit that enforces CCFI and a secure call mechanism to block buffer overflows and detect control-flow tampering via a shadow stack, with ~20k GE reported and minimal runtime overhead. Counters implemented include jittered execution, dummy instructions, ECC and glitch detection, bus polarity inversion, performance counters, and digital sensors for EM/fault attacks. Platform support includes Ibex, cv32 and IEX variants; an integrated secure element with this core achieved ASIL-B certification and FIPS/CC alignment and protection-profile testing.
AI-written summary · about
chapters (9)
- 0:00Introduction to Secure-IC
- 0:54Integrated secure elements
- 2:26Importance of CPU security
- 3:57Core security requirements
- 5:46Hardening the RISC-V core
- 8:43Cyber escort and integrity
- 10:57Configurable design strategy
- 12:29Collaboration and conclusions
- 14:09Q&A session
related talks
09mThe Future of Embedded Security with RISC-V
27mControl Flow Integrity on RISC-V
47mA Security RISC? The State of Microarchitectural Attacks on RISC-V
13mRISC-V: Securing the Future of Open Source Computing
19mAn Open Source Approach to System Security
20mArchitectural Extensions for a RISC V Processor for Embedded Security
20mRISC-V open designs and contributions to hardware security research and development activities
35mControl Flow Integrity on RISC-V Linux