Control Flow Integrity on RISC-V
summary
Hardware implementation of control‑flow integrity on RISC‑V enforces Call/Return checks and a shadow stack in silicon, using a parallel metadata cache that stores expected return targets and nine‑entry metadata blocks to validate indirect branches. Prototype runs at full speed with no measurable execution slow‑down, prevents typical buffer‑overflow and ROP attacks, and flags mismatches on reset. Design also addresses external flash boot and notes remaining gaps: formal verification and mitigations for Spectre‑style timing leaks.
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chapters (9)
- 0:00RISC-V and hardware security
- 3:01Hardware security importance
- 7:02Secure boot and isolation
- 11:01Embedded flash security challenges
- 15:39Control Flow Integrity on RISC-V
- 18:55Hardware caches and timing attacks
- 22:30Processor security design
- 25:04Future of trusted hardware
- 26:16Q&A
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