Challenges in Open-source RISC-V Implementations: Differentiation & Customization
summary
A RISC-V IP family called BK3 BK5 BK7 is fully configurable and claimed verified (VM-based coverage and verification plans) and the mandatory RISC-V subset is about 40 instructions. An EDA tool called ImageCoral ADL plus studio generators accepts C-like descriptions of custom instructions and microarchitecture tweaks, then outputs readable RTL (SystemVerilog/VHDL), an LLVM-based toolchain, and UVM testbenches, enabling added DSP opcodes that accelerate codecs and shipable cores used in silicon and university programs.
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chapters (11)
- 0:00Intro
- 1:31Bk: Customizable RISC-V Cores
- 4:03Configuration and Custom Extensions
- 5:13What is Codasip Studio?
- 7:17Bk Core Customization with Codasip Studio
- 8:15Open Source Hardware-Promises and Hopes
- 9:50Open Source Hardware - Challenges
- 11:53Challenges - Possible Solutions
- 13:55Open source costs
- 14:36Example: Automotive and Open Source HW
- 15:40Conclusion
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