Open Source computer architecture research at the BSC

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" summary

Barcelona Supercomputing Center produces a first silicon RISC‑V ASIC: a 5‑core RV64 microprocessor, five‑stage pipeline, fully in Verilog, integrated into a Rocket-based SoC and taped out as part of an MPW. Fabrication uses SMC 65 nm, 2×2 mm die, 200 MHz target, chips returned recently. Bring‑up uses a Kintex FPGA via an MMC connector to emulate memory controllers; a JTAG/back‑ring co‑simulation with Spike enables step‑by‑step compare and debug. Open RTL/IP and CI help, analog IP and foundry libraries remain closed and limiting.

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" chapters (8)

1. 0:00Start
2. 0:36Introduction
3. 4:11Block Diagram
4. 5:28Jtag Models
5. 6:55Tools
6. 7:47Proprietary Tools
7. 10:25Conclusion
8. 14:05Contact Information

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