Taking nextpnr to the next level!
summary
nextpnr becomes a production-ready place-and-route for Lattice ECP5 with 29 contributors since May 2018, replacing simulated-annealing placement with the HeAP analytical placer that runs up to ~50× faster on some designs, adding multi-threaded timing analysis (upstream pending) and low-level high-speed IO support. Builds demonstrably include Linux-capable VexRiscv and Rocket systems with DDR3 and Gigabit Ethernet; partial reconfiguration and experimental Xilinx flows (Project X-Ray, RapidWright) also work as proofs of concept.
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chapters (12)
- 0:00Introduction
- 1:05Synthesis
- 1:35Updates
- 2:54Analytical Placement
- 3:52Traditional FPGA Placement
- 4:25Run Time
- 4:54CP5 Support
- 5:51Development Board
- 6:11Xilinx Flows
- 8:40Future plans
- 10:47How you can help
- 11:44Patreon
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