ASICone, from Verilog to GDSII with open source tools
summary
ASICone attempts a full tape-out of a RISC‑V 32‑bit microcontroller on X‑Fab 180nm CMOS using only open‑source tools. The team actually generates standard cells and a pad ring, instantiates the chip with Chisel, does synthesis with Yosys, uses Magic for layout and ngspice+Octave for analog simulation, and builds a working bandgap analog IP that reaches post‑layout verification. Analog flow ends up 3–4× slower than commercial tools; missing pieces are power planning, clock synthesis, sign‑off and automated DRC/PDK translation, and PDK NDAs block open analog IP sharing.
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chapters (29)
- 0:00Introduction
- 0:18Team
- 2:47Our experience
- 3:19The problem
- 4:59Cost
- 5:41DARPA
- 6:34Onchip
- 7:31Open Source Ecosystem
- 10:32Raven
- 12:07Cord
- 13:03Bankup
- 14:43Design to tape out
- 18:12Analog IP
- 19:45Tools
- 20:18Honorable mentions
- 21:31Analog flow
- 24:36Hierarchical approach
- 25:20Postlayout
- 26:07Open Source Tools
- 28:10Tcell Generation
- 29:04Standard Cell Generator
- 31:12Open Source Issues
- 32:55Final Result
- 33:39Analog Issues
- 35:16DRC Verification
- 36:26Missing tooth
- 36:52DARPA tools
- 37:32Conclusion
- 38:59How much work can be reused
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