SystemVerilog compatibility Test-Suite
summary
An open-source SystemVerilog test suite systematically exercises the standard with hundreds of compact test cases and runs each case across multiple simulators to produce a tool-independent test suite and a visible metrics matrix of pass/fail coverage. Many tests target specific syntax and semantic clauses; some existing cases contain typos or gaps and need completion. Plan includes importing real projects as end-to-end external projects to validate whole-tool behavior and driving tool improvements toward full coverage of syntax and semantics.
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