Verifying All the Flexibility of RISC-V within SoC DV Test Plans

on YouTube ↗24m

" summary

Updates to the RISC-V compliance suite use the riscvOVPsim reference model and integrate with open instruction generators (Google ISR) and UVM flows to run step-and-compare SystemVerilog encapsulation against RTL. Empiric results: the baseline 32I repo has 48 hand tests that cover ~35% of extended cases, millions of random runs reveal masked bugs, and vector testing expands to 7000 vector tests across ~500 opcodes. Recommendation is step-and-compare for faster divergence detection versus signature-only checks.

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" chapters (6)

1. 0:00Introduction to RISC-V verification
2. 1:03Verification vs compliance testing
3. 7:47Reference models for RISC-V
4. 12:15Processor IP verification methods
5. 20:21SoC-level verification challenges
6. 21:45Wrap-up and key takeaways

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