Keynote: State of the Union
summary
RISC‑V claims rapid industry adoption in five years and now manages the ISA spec, golden model and compliance tests while supporting both open and commercial cores; there are more commercial IP providers than any other ISA in history. Design specifics that enabled software ports include native 4 KB page size, little‑endian choice, and a weak memory model with TSO extension. Ongoing engineering priorities: finish verticals, add cache maintenance ops, evaluate a double‑word CAS, and keep frozen base modules to preserve stability and compatibility.
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chapters (9)
- 0:00Welcome and introductions
- 1:05Risk-V project overview
- 2:47Ecosystem and architecture
- 5:34Evolution of project goals
- 6:58Founding goals and non-goals
- 9:07Foundation and industry impact
- 11:51Current community priorities
- 14:11Modern software-driven goals
- 17:52Strategy for future success
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