Keynote: RISC-V in Academia and Education
summary
A plan to infuse RISC-V into core curricula claims measurable progress: 30 artifacts online and a professional training partner program launched in August with four training partners. It names practical pain points—poor comparability of research results, unstable open projects, and uneven board availability—and shows remedies: a VS Code Venus simulator extension that lets students step, change registers and debug on any platform, and use of SweRV EL2 with microarchitecture traces to teach pipeline timing. Outcomes are working labs and growing community resources.
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