Semidynamics New Family of High Bandwidth Vector-Capable Cores

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" summary

SemiDynamics unveils two RISC‑V cores: Avispado 220, a two‑wide in‑order core that sustains 64+ outstanding misses past L1 and implements RVV 1.0 support, and Atrovito 220, a two‑wide out‑of‑order core with 128+ outstanding misses tolerance and a larger branch predictor and renaming/PRF. An Open Vector Interface on GitHub exposes issue/credit/completion and load/store/mask channels with VM coherency so third parties can attach custom vector units; one core is already used in the European Processor Initiative RISC‑V accelerator.

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" chapters (9)

1. 0:00Introduction and company overview
2. 1:25High bandwidth core concept
3. 4:54Vector gather instruction demo
4. 6:58Comparison with other cores
5. 8:43Applications and use cases
6. 12:59Open vector interface explained
7. 17:15Avispado 220 core details
8. 19:42Atrovito 220 core details
9. 21:29Summary and licensing

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