An Automated Scalable RISC-V Cache Coherency Verification Project
summary
A scalable cache coherency app generates deterministic tests from a coherency protocol graph and runs them as bare-metal C and UVM workloads, scoreboarding every read and measuring state/transition coverage. The planner translates protocol state machines via automated protocol-to-graph translation, co-schedules false- and true-sharing, varying sizes, snoop sources and power states, and reports profiling/debug steps. Tool authors claim about 10^45 scenarios in the space, show big coherency traffic storms in cycle-accurate sim, and report higher coverage and bugs found sooner in simulation and post-silicon.
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chapters (15)
- 0:00Introduction to project
- 1:06Cache coherency verification challenges
- 2:14Planning algorithm for test generation
- 4:19Technology deployment levels
- 5:45Verification metrics and graphs
- 7:09Cache line state space coverage
- 10:17Multi-core sharing and snoops
- 12:01Operation sizes and false sharing
- 13:27Cross cache line boundaries
- 14:50Memory ordering tests
- 15:54Power management scenarios
- 16:38Memory workload stress tests
- 17:19Test case effectiveness results
- 18:01Case studies and results
- 19:27Summary and future work
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