Adnan Hamid
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| title | conference | date |
|---|---|---|
| RISC-V System-level Certification from Verification Foundations | RISC-V Summit North America 2025 | 2025-10-22 |
Covers concrete system-level tests and a toolchain that synthesizes C+ASM tests and TBX testbenches from graph models, exercising atomics, cache coherency, AIA… | ||
| Demo: RISC-V AIA Expanding Interrupts: Applications, Implementation and Verification | RISC-V Summit North America 2025 | 2025-10-22 |
Demonstrates a test-suite synthesis flow that configures the RISC-V AIA (per-hart MSIC per hart and system APLIC), generates C with inline asm plus a TBX… | ||
| RISC-V SoC Coherency: Dealing with Unique RISC-V Coherency Issues | RISC-V Summit 2022 | 2022-12-13 |
Overview of RISC‑V nested virtualization with the Hypervisor (H) extension: architecture exposes HS mode plus VS/VM user modes, two‑stage guest→host… | ||
| RISC-V SoC Coherency: Dealing with Unique RISC-V Coherency Issues | RISC-V Summit 2022 | 2022-12-13 |
Breker’s Portable Stimulus test generator synthesizes self-checking coherency tests from a cache-protocol state machine, co-scheduling hundreds of sequences to… | ||
| An Automated Scalable RISC-V Cache Coherency Verification Project | RISC-V Global Forum 2020 | 2020-09-03 |
A scalable cache coherency app generates deterministic tests from a coherency protocol graph and runs them as bare-metal C and UVM workloads, scoreboarding… | ||
| nothing matches | ||