Demo: RISC-V AIA Expanding Interrupts: Applications, Implementation and Verification

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" summary

Demonstrates a test-suite synthesis flow that configures the RISC-V AIA (per-hart MSIC per hart and system APLIC), generates C with inline asm plus a TBX transactor, and injects PCIe MSIs or wired interrupts to exercise interprocessor interrupts. A concrete test sends minor ID 0x1F from hart0 to hart3, waits for the trap handler (the test hangs if the interrupt is lost), storms the system with concurrent messages and other instructions, and checks for lost or spurious interrupts while reporting failures and coverage.

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" chapters (7)

1. 0:00Introduction and speaker intro
2. 0:44What is RISC-V AIA
3. 3:41AIA components overview
4. 6:50Interrupt routing flows
5. 10:30Breer's verification approach
6. 13:39Debug and coverage strategy
7. 15:26Q&A on AIA vs Clint

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