Automated Certification and Benchmarking for RISC-V Architectures
summary
Claims a reproducible benchmarking pipeline that cuts toolchain setup from two–three days to about half a day (≈3x faster) and automates ~85% of benchmarking tasks, using Docker-based containers to lock toolchain versions, a metadata-enabled database for traceability, and hybrid execution across simulation and FPGA to collect latency, jitter, IPC and determinism metrics. Targets real-time RISC-V cores with ISO 26262 alignment, provides evidence-ready reports, and plans a public release with automated compliance checks early next year for simulation-to-FPGA parity and certification-ready outputs.
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chapters (14)
- 0:00Introduction and speaker background
- 1:30Quintaris organization and mission
- 2:15Market challenges in RISC-V certification
- 4:44Benchmarking challenges for RISC-V
- 5:04Test automation framework overview
- 6:30Framework architecture and workflow
- 8:39Problems solved by the framework
- 10:27Memory characterization use case
- 11:53Certification alignment and standards
- 12:59Advantages and efficiency gains
- 13:19Current framework capabilities
- 13:43Roadmap and future plans
- 14:50Long-term vision for RISC-V adoption
- 15:10Closing and collaboration call
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