AI-Ready RISC-V Using On-Chip Monitoring for Performance & Reliability at Scale
summary
ProteanTecs IP embeds tiny on‑chip margin agents under real logic paths and Andes AX45MPV supports up to 2048-bit vectors; a prototype 5 nm chip runs about 500 margin agents that monitor timing margin and trigger firmware AVS controls, yielding up to 14% power reduction in experiments that correlate to ~18% lifetime extension. The system flags marginal test units for scrapping or extra screening, detects IR drop events to restore safe voltage, and provides degradation indices for predictive maintenance and silent‑data‑corruption detection.
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chapters (10)
- 0:00Introduction and speakers
- 0:24Why RISC-V matters for AI
- 3:39Andes RISC-V product families
- 5:30Proantex overview and use cases
- 7:39Power challenges in AI
- 8:22Silent data corruption problem
- 9:05On-chip margin monitoring technology
- 11:30Adaptive voltage scaling demo
- 14:41Silent data corruption solutions
- 17:12Summary and Q&A
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